Symmetric Multiprocessing System

Symmetric Multiprocessing System is a multi-processor based Architecture where there are two or more identical processors with a shared address space. This means that each processor in Symmetric Multiprocessing System has the same (physical) address and the same alloted memory or the same peripheral registers. Most multiprocessor systems today are of Symmetric Multiprocessing architectures.

 

Basics on Symmetric Multiprocessing System

 

ASymmetric Multiprocessing System or architecture enables the ongoing processes dynamically on all the available processors to distribute – however in the asymmetric multiprocessing, each CPU task will be assigned to (for example, CPU0 handles operating system calls and CPU1 the user processes), since not all tasks on each processor can be performed. There are also application domains (control systems with hard real-time requirements ), in which a static mapping of processes is advantageous on Symmetric Multiprocessing architecture.

 

Details of Symmetric Multiprocessing System

 

 

Symmetric multiprocessing is used since the late 1980s, the standard architecture for multi-processor machines is with up to 16 CPUs. The requirement that each CPU can execute any process, results in larger systems – it means that the memory is the bottleneck. With each additional CPU the relative performance gain decreases as the storage subsystems can not deliver the data fast enough to utilize all the available CPUs.

Another problem with the Symmetric Multiprocessing System’s CPU is hopping – change of the processes constantly between CPUs. Normally this would not be a problem, but as often CPUs with very large, multi-tiered SMP systems, caches are used to reduce the already described utilization of the storage system, the rapid change of the running processes also leads to a performance degradation by so-called cache thrashing. This refers to the constant change of the cache contents through different processes, which are usually accessible in different ranges of data. However, this can be counteracted the effect by assigning a higher affinity of the processes to the respective executing CPU.

 

In further developments, such as the NUMA (Non-Uniform Memory Architecture), these problems are reduced. In principle, all modern CPU architectures are more or less suitable for use in SMP systems. There are differences only in the required additional hardware and the expected increase in performance per CPU. While with some CPU variants already relatively simple 2 – or 4-way systems can be built, since the CPU bus is already a part of the required functionality is implemented (for example, all systems with Intel GTL + bus), in other systems relatively expensive point-to-point connections is required (AMD K7 and HP Alpha with EV6 bus). Currently, the manufacturers go for the required memory controller integration in the CPU. In turn, it makes sense to integrate several processor cores on the chip, since a single core can not always utilize the available bandwidth of the memory system. Such multi-core processors should not use hyperthreading -enabled processors to be confused, because this is completely independent cores with associated infrastructure (L1/L2-Caches, FPU is, etc.).

 

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