Previously, we discussed about UART. What is I²C Protocol? I squared C (also pronounced as I-two-C) or I²C is a bus serial communication protocol designed by Philips for home automation and home electronics applications. Since 2006, licensing fees not needed to implement the I²C protocol. Fees needed to obtain I²C slave addresses allocated by NXP. I²C can connect a microprocessor and various circuits. In computing, a bus means a communication system which transfers data between components inside a computer, or between two or multiple computers. What is relevance of I²C in Arduino? Previously we talked about RX TX in Arduino and serial connection (in the article on UART) too. Each I²C bus consists of two signals – SCL (clock signal) and SDA (data signal). You noticed them on various Arduino modules as pins. We can use it by including Wire library.
What is I²C Protocol?
From our previous discussions, serial ports are asynchronous. So no clock data is transmitted. Hence the devices using serial ports must have agreement of time on a data rate. Two devices need to have clocks which are close to the same rate. Too much difference will cause garbled data. Asynchronous serial ports demands hardware – UART, which is somewhat complex. Also asynchronous serial ports inherently suited to communications between only two devices. There is no theoretical limit to asynchronous serial communications, but most UART devices only support a certain set of fixed baud rates.
I²C is a half-duplex bidirectional synchronous serial bus, where several devices, masters or slaves, can be connected to the bus. Exchanges always take place between a single master and one (or all) slave(s), always on the initiative of the master (never from master to master or from slave to slave). However, nothing prevents a component from passing from master to slave status and vice versa. The connection is made via two lines:
SDA (Serial Data Line): bidirectional data line,
SCL (Serial Clock Line): bidirectional synchronization clock line.
The 2 lines are pulled at voltage level VDD through pull-up resistors. Maximum number of devices is limited by the number of available addresses, 7 address bits and one R/W bit (read or write), ie 128 devices, but it also depends on the bus capacity (on which depends the maximum speed of the bus). It should be noted that addresses are reserved to broadcast messages and that many addresses are already allocated by manufacturers which greatly limits the number of devices (a variant of 10-bit addressing also exists).
In Ultra-fast mode (UFm) mode, the bus is unidirectional, so there can only be one master. The 2 lines are renamed USCL (clock line) and USDA (data line), and the master side, they are always output and push-pull type. This mode has limited use.
The equipment connected to the bus is connected via open collector on both SDA and SCL lines. The equipment is thus wired on the bus by the principle of “AND wired”, which means that in case of simultaneous emission of two devices, the value 0 overwrites the value 1. So we can say:
the logical state “0” or “LOW” is the “dominant” state,
the logical state “1” or “HIGH” is the “recessive” state.
When the bus is not in use, it is high (through pull-up resistors).
Dominant or “0” or “LOW” : from -0.5 V to 0.3x VDD
Recessive or “1” or “HIGH” : 0.7x V DD to VDD
There are five transmission speeds:
Standard mode (Sm) ≤ 100 kbit/s,
Fast mode (Fm) ≤ 400 kbit/s,
Fast plus mode (Fm+) ≤ 1 Mbit/s,
High-speed mode (Hs-mode) ≤ 3.4 Mbit/s,
Ultra-fast mode (UFm) ≤ 5 Mbit/s, unidirectional only.
Above things we discussed is around physical layer. I²C defines basic types of transactions, each of which begins with a START and ends with a STOP:
Single message where a master writes data to a slave.
Single message where a master reads data from a slave.
Combined format, where a master issues at least two reads or writes to one or more slaves.
To initiate the address frame, the master device leaves SCL high and pulls SDA low.
The address frame is always first in any new communication sequence. For a 7-bit address, the address is clocked out most significant bit (MSB) first, followed by a R/W bit indicating whether this is a read (1) or write (0) operation.The 9th bit of the frame is the NACK/ACK bit.
After the address frame has been sent, data can begin being transmitted. During data writing operation, the value on SDA not changed to avoid imposing false stop condition.
Once all the data frames have been sent, the master will generate a stop condition. Stop conditions are defined by a 0 to 1 (low to high) transition on SDA after a 0 to 1 transition on SCL. In this situation, SCL remains high.
There is official website to learn more in-depth and other layers :
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