Reduced Instruction Set Computer (RISC) is a design philosophy for computer processors. The design goal was to dispense with a complex instruction set that was convenient for assembly programming in favor of instructions that were easy to decode and quickly execute. This also allowed for higher clock speeds.
The design philosophy opposite to RISC is called the Complex Instruction Set Computer (CISC). In modern times, the distinction between RISC and CISC has largely lost its importance. Former RISC processor families have now also included more complex instructions, CISC processors have received RISC-like design components since the mid-1990s and are also superscalar. The decoding of instructions takes up only a small part of the chip area, regardless of RISC or CISC. The main surface area of the chips is now occupied by processing units that have only appeared in processors since the early 1990s.
Typical Characteristics of RISC Processors
There is no formal definition of the same. The majority of RISC processors have the following features:
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Superscalarity
The “actual command execution” usually only takes 1 clock cycle per instruction.
One command is started per bar, and a (previous) command is terminated in each bar. Decoding is done without microcode through a hardwired network. A classic RISC processor executes commands in four cycles: Fetch, Decode, Load, Execute. There is always a command in each of these levels.
Load store architecture
In a load-store architecture, only load and store commands access memory. All other commands work exclusively with register operands and literals. These load and store commands do not have complex address modes, instead the addresses are calculated in freely usable registers. However, only a few RISC CPUs have a classic load-store architecture, most allow a memory operand.
Large number of open-to-use registers and three-address code
To enable the compiler to generate code efficiently and optimize programs, RISC processors have a large number of free-to-use registers (typically 16 or 32) and instructions in three-address code. Commands in the three-address code have one destination and two source registers. The Berkeley RISC processor and its descendants also have register windows that allow a particularly large number of registers and speed up the call of subroutines.
Fixed-length, low-format commands
All commands are the same length and there are only a few command formats. This means that the position of opcode, register operands and literals is the same for almost all instructions, which makes decoding much easier and thus faster. Typical are 32-bit wide command words and five different command formats. These RISC architectures use variable instruction lengths of 16 and 32 bits to shorten the program code.
