Von Neumann Architecture : The Reference Model for Computer

Von Neumann architecture (VNA) is a reference model for computer, according to which a common memory both for the computer program instructions and other data is hold. Von Neumann systems includes the Flynnschen classification to the class of SISD architectures (Single Instruction, Single Data), in contrast to parallel processing.
Von Neumann architecture is the basis for the operation of most known computers of today. It is named after the Austrian-Hungarian mathematician named John Von Neumann, whose main work was published about 1945. It sometimes also called with the same U.S. university’s named – Princeton Architecture.


Von Neumann Architecture : Development and Concept


Von Neumann in 1945, described the concept in the first unpublished paper “First Draft of a Report on EDVAC” in the context of the construction of the EDVAC computing machine. It was revolutionary in its day, as previously developed computers were attached to a solid program that was connected either to hardware or punch cards had to be read. With the Von Neumann architecture, it was then possible to make the changes to programs very quickly and without making any changes to the hardware or to run different programs in quick succession.

Most of the computers in use today are based on the fundamental principle of Von Neumann architecture, i.e. their properties are similar to those of a VNA. However, this typically no more that they are structured like a simple VNA – VNA with the few functional groups. Over time, many of the originally conceived simple VNA computer architectures such as the x86 architecture, differentiated beyond and developed to be more complex. This was done in order to achieve performance gains, but without breaking the easily manageable VNA model, ie terms of software compatible to be able to stay to continue to use this to its advantage.

With the trend of increasing number of parallel processing units ( multi-core processors ) and buses (e.g. HyperTransport ) are always becoming complex and difficult to implement the compatibility. It is therefore to be expected that in the foreseeable future, a paradigm to shift to a different, parallel architectural model which will be required to achieve performance gains in computer architectures.

The Von Neumann architecture is a circuit concept for the realization of universal computer (Von Neumann computer or VNR). They realized through all the components of a machine. However, their systematic breakdown in the corresponding functional groups allows the usage of specialized binary switching stations and thus a more efficient structuring of operations. But, it remains in principle, even on a machine with pure Von Neumann architecture. The same applies to all high-level languages?, by a compiler or interpreter are mapped to the binary representation. Although they simplify the handling of the operations, but do not include the extension specified by the machine semantics. This is illustrated by the fact that the translation from a high level language into the binary representation is in turn made without the need of user’s interaction.


Von Neumann Architecture : Limitations


Von Neumann Architecture

Bottleneck of the Von Neumann architecture refers to the architectural facts that the connection system (data and instruction) bus is the bottleneck between the processor and the memory. Proceeding of the Von Neumann bottleneck id the only one thing at a time. Since a Von Neumann Architecture, in contrast to Harvard architecture has only one common bus for data and instructions to be used, this limits the maximum transferable amount of data need to be split. In early computers, ??the CPU was the slowest unit of the computer, i.e. the data delivery time was only a small proportion of the total processing time for an arithmetic operation. For some time, however, the CPU processing speed grew significantly faster than the data transfer rates of buses or memory, which exacerbated the impact of Von Neumann bottleneck.

One of the most important competitive architectures is the Harvard architecture with a physical separation of control and data memory is accessed via separate buses, that is, independently. The advantage of this architecture is that instructions and data load at the same time or may be written, the potential Von Neumann bottleneck can be avoided. The potential disadvantage compared to the Von Neumann architecture is the all parallel system resulting in a non-deterministic program execution.


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