RISC-V is an instruction set architecture (ISA) based on the design principle of the Reduced Instruction Set Computer (RISC). It is an open standard that is subject to the permissive BSD license. This means that RISC-V is not patented and can be used freely. Thus, anyone is allowed to design, manufacture, develop and sell RISC-V microprocessors (open source hardware). Numerous companies offer or have announced RISC-V hardware.
It is available in 32 bit, 64-bit, and 128-bit versions. Its specifications are open and can be used freely by teaching, research and industry. Specifications are openly ratified by the international developer community
RISC-V is implemented in different SoCs, for the embedded, connected objects (supported by different real-time systems or for the embedded, such as Arduino, FreeRTOS, HarmonyOS etc, light computers in the form of SBCs, usually with Linux (Debian, Fedora, Gentoo, Ubuntu) or variants of OpenWrt, as well as Haiku, FreeBSD, NetBSD and OpenBSD. Xv6, a UNiX designed for educational purposes for system development students also runs on this architecture.
The design of the processor began in 2010 at the University of California Berkeley, in the United States, was initially intended for study and research, but has become a de facto open architecture standard in the industry. The goal of this project is to make an open standard of microprocessor instruction set, like the TCP/IP standard for networks or UNIX for operating systems, the processor architecture being for the moment still closed, restricting progress, implementations or support in operating systems.
The ESP32 C3 has a single 160 MHz RISC-V core and includes most of the peripheral set of a typical ESP32 with Tensilica Xtensa LX6 microprocessor.
Unlike other academic designs, which are usually optimized for simple explanation, the RISC-V instruction set was designed for practical application in computers. It has features that increase computer speed, but still reduce costs and energy consumption. This includes a load/store architecture, bit patterns to simplify the multiplexers in a CPU, simplified standards-based floating-point numbers, an architecture-neutral design, and setting the most significant bit to a fixed position to speed up sign expansion.